The need for accurate yield prediction is increasing for estimating productivity and production costs to secure high revenues in the semiconductor industry. Corresponding to this end, we introduce new spatial modeling approaches for spatially clustered defects on an integrated circuit (IC) wafer map. We use spatial location of an IC chip on the wafer as a covariate on corresponding defects count listed in a wafer map. Analysis results indicate that yield prediction can be greatly improved by capturing spatial features of defects. Tyagi and Bayoumi's (1994) wafer map data are used to illustrate the procedure.

Abstract
 1. INTRODUCTION
 2. SPATIAL MODELING OF DEFECTS ON A WAFER MAP
 3. ZERO-INFLATED POISSON REGRESSION MODEL
 4. PRACTICAL EXAMPLE
 5. CONCLUSION
 REFERENCE

• Suk Joo Bae(Hanyang University)
• In-Jae Jeong(Hanyang University)
• Chang Wook Kang(Hanyang University)