본 연구에서는 silicalite-1 제올라이트 분리막 합성 시에 종결정 코팅용액 pH 변화가 제올라이트 분리층 미세구조에 미치는 영항을 고찰하였다. 75 nm 크기로 합성된 종결정은 에탄올에 분산된 후 침지코팅법으로 지지체 표면에 코팅되었으며 분산용액의 pH는 2.2, 7.0, 9.3으로 조절되었다. pH가 7인 경우, 균일하고 두께가 3~4 μm인 silicalite-1 제올라이트 분리층이 형성되었고 분리층 결정입 크기는 100 nm로 미세하였다. 반면, pH가 2.2와 9.3인 경우, 분리층 두께가 얇고 불완전하였으며 분리층 결정입 크기도 약 1 μm로 조대하였다. pH 7에서 완전한 제올라이트 분리층이 형성된 것은 침지코팅 중에 지지체와 종 결정이 서로 다른 부호의 전하를 가져 정전기적 인력이 작용하여 균일하고 조밀하며 두껍고 다층의 종결정 코팅층이 형성되었 기 때문이었다. 반면에 pH가 2.2와 9.3인 경우, 침지코팅 중에 지지체와 종결정이 서로 같은 부호의 전하를 가져 정전기적 반 발력이 작용하기 때문에 불완전한 덮힘에 의하여 불완전한 분리층이 형성된다고 판단되었다. 결론적으로, 종결정 코팅용액의 pH가 silicalite-1 제올라이트 분리층의 두께, 결정립 크기 등 미세구조를 결정하는 중요한 인자임을 확인할 수 있었다.

본 연구에서는 종결정 코팅층이 NaA 제올라이트 분리막 형성에 미치는 영향에 대하여 고찰하였다. NaA 제올라이트 분리막은 평균입경 100 nm 종결정을 다공성 α-알루미나 표면에 진공여과 코팅하고 100˚C에서 24시간 수열처리하여 합성되었다. 이때 지지체 표면에 분포된 종결정 양을 조절한 후 형성된 NaA 제올라이트 분리층의 두께와 결정입 크기 등 미세구조에 미치는 영향에 대하여 고찰하였다. 종결정 코팅 양은 지지체를 통과한 종결정 수용액의 여과 양을 조절하여 제어하였다. 종결정을 단일층으로 코팅한 후 합성하였을 경우, 코팅 양이 증가함에 따라 분리층 단면에서의 두께와 균일도는 증가하였으며, 표면에서의 결정입 크기는 감소하면서 균일도는 증가하였다. 반면, 종결정을 다층으로 코팅한 후 합성하였을 경우, 균일한 분리층을 형성하였지만 단일층으로 코팅된 경우에 비하여 불균일하였으며 두꺼운 분리층이 형성되었다. 균일하고 초박형의 결함이 없는 제올라이트 분리층을 형성하기 위해서는 종결정을 균일하고 단일층으로 코팅하여야 함을 알 수 있었다. 본 연구로부터 종결정의 코팅 상태가 이차성장에 의한 NaA 제올라이트 분리층의 미세구조를 결정하는 중요한 인자임을 확인할 수 있었다.

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

The formation of high-quality polycrystalline silicon (poly-Si) on relatively low cost substrate has been an important issue in the development of thin film solar cells. Poly-Si seed layers were fabricated by an inverse aluminum-induced crystallization (I-AIC) process and the properties of the resulting layer were characterized. The I-AIC process has an advantage of being able to continue the epitaxial growth without an Al layer removing process. An amorphous Si precursor layer was deposited on Corning glass substrates by RF magnetron sputtering system with Ar plasma. Then, Al thin film was deposited by thermal evaporation. An SiO2 diffusion barrier layer was formed between Si and Al layers to control the surface orientation of seed layer. The crystallinity of the poly-Si seed layer was analyzed by Raman spectroscopy and x-ray diffraction (XRD). The grain size and orientation of the poly-Si seed layer were determined by electron back scattering diffraction (EBSD) method. The prepared poly-Si seed layer showed high volume fraction of crystalline Si and<100> orientation. The diffusion barrier layer and processing temperature significantly affected the grain size and orientation of the poly Si seed layer. The shorter oxidation time and lower processing temperature led to a better orientation of the poly-Si seed layer. This study presents the formation mechanism of a poly seed layer by inverse aluminum-induced crystallization.

This study was carried out in each three study areas of Pinus densiflora community and Quercus mongolica community from March 5th, 2008 to October 15th, 2010 to analyze the relationship between seed bank and the actual vegetation of the lower layer. Based on the relationship between the lower layer of actual vegetation and the germination of seed bank, all of three study areas, the similarity of the actual vegetation of the lower layer and seed bank were high in Plot 1 (84.62%) and Plot 3 (89.91%). As for Quercus mongolica community, the similarity was high between the actual vegetation of the lower layer and seed bank in Plot 4 (82.24%) and Plot 6 (89.47%). Especially, the germination of the pine seed banks in the Pinus densiflora community compared to other tree species appeared in all. In Quercus mongolica community, Quercus mongolica did not appear among the seeds germinated in the seek bank, but the other tree species constituting the under layer of the community. In case of the restoration based on the actual vegetation, it is desirable to sue the lower layer of vegetation as the model for the making of its alternatives for restoration works of the species.