Fault-Tolerant Analysis of Redundancy Techniques in VLSI Design Environment - koreascholar

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Fault-Tolerant Analysis of Redundancy Techniques in VLSI Design Environment KCI 등재

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URLhttps://db.koreascholar.com/Article/Detail/21905

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한국산업경영시스템학회지 (Journal of Society of Korea Industrial and Systems Engineering)

Vol. 22 No. 53 (1999.12)
pp.111-120

한국산업경영시스템학회 (Society of Korea Industrial and Systems Engineering)

저자

Cho, Jai Rip(Dept, of Industrial Engineering, Kyung-Hee University, Korea)

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