This paper addresses order-lot pegging issues in the supply chain of a semiconductor business. In such a semiconductor business (memory or system LSI) order-lot pegging issues are critical to achieving the goal of ATP (Available to Promise) and on-time production and delivery. However existing pegging system and researches do not consider capacity limit on bottleneck steps. This paper presents an order-lot pegging algorithm for assigning a lot to an order considering quality constraints of each lot and capacity of bottleneck steps along the entire FAB. As a result, a quick and accurate response can be provided to customer order enquiries and pegged lot lists for each promised orders can be shown transparently and short or late orders can be detected before fixing the order.