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0.1 μm SOI-MOSFET의 적정 채널도핑농도에 관한 시뮬레이션 연구 KCI 등재 SCOPUS

Investigation of Optimal Channel Doping Concentration for 0.1 μm SOI-MOSFET by Process and Device Simulation

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한국재료학회지 (Korean Journal of Materials Research)
한국재료학회 (Materials Research Society Of Korea)
초록

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and thechannel depth (D) at 3:1 or larger is known to be critical in preventing deleterious short-channel effects. Inthis study, n-type SOI-MOSFETs with a channel length of 0.1µm and a Si film thickness (channel depth) of0.033µm (L:D=3:1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioningtransistors on the very thin Si film, a protective layer of 0.08µm-thick surface oxide was deposited prior tothe source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron dopingconcentration of the Si film, in which the device channel is formed, was used as the key variable in the processsimulation. The finished devices were electrically tested with a Medici device simulator. The result showedthat, for a given channel doping concentration of 1.9~2.5×1018cm−3, the threshold voltage was 0.5~0.7V, andthe subthreshold swing was 70~80mV/dec. These value ranges are all fairly reasonable and should form a‘magic region’ in which SOI-MOSFETs run optimally.

저자
  • 최광수 | Choe, Kwang-Su