For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

1. 서 론
 2. 관련 연구
  2.1 DDS를 이용한 PLL 주파수합성기 모델링
  2.2 PLL 주파수합성기 모델 Simulation
  2.3 PLL 주파수합성기가 적용 된 데이터링크시스템 블록도
  2.4 PLL 주파수합성기 제작 및 측정
 3. 결 론
 5. References

• 권상철(에이스안테나 방산 연구소) | Sang-Chul Kwon Corresponding Author
• 강경식(명지대학교 산업경영공학과) | Kyung-Sik Kang