As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

많은 선행 연구에서는 무연 차폐재를 제작하기 위하여 몬테카를로 시뮬레이션을 통해 방사선 차폐 능력과 경량화에 대한 가능성을 제시하고 있다. 하지만, 이는 바인더 및 미세 기공에 대한 구현이 어렵기에 제품화 공정에 필요한 정보를 충분히 제공하지 못하는 실정이다. 이에 본 연구에서는 제품화 공정에 요구되는 겔 페이스트에 대한 정보를 사전에 제공하기 위하여 스크린 프린팅 공법을 활용하여 충전율에 따른 방사선 차폐 능력에 대한 결과를 제시하였다. 본 연구에서는 방사선 차폐 능력을 평가하기 위해 IEC 61331-1: 2014와 KS A 4025에 부합하도록 실험 환경을 설계하였으며, 방사선 조사 조건은 KS A 4021 규격을 준용하여 총 여과 2.0 mmAl로 여과된 100 kVp를 이용하였다. 본 연구 결과, TVL를 기준으로 Pb 1270 μm, BaSO4 3035 μm, Bi2O3 1849 μm, WO3 2631 μm에서 근사한 값으로 분석되었다. 또한, 충전율은 BaSO4 38.6%, Bi2O3 27.1%, WO3 30.15%로 분석되었다. 하지만, 차후 저온고압 성형을 적용한다면 충전율을 높이면서도 기공률을 낮춤으로서 방사선 차폐 능력의 개선이 충분히 가능할 것으로 기대된다.