논문 상세보기
pp.511-522
Through-silicon via (TSV) filling is indispensable for three-dimensional semiconductor packaging. Conventional processes rely on PVD (physical vapor deposition) or ALD (atomic layer deposition) seed layer deposition followed by copper electroplating, but these approaches face limitations in productivity and conformality. ALD and ELD (electroless deposition) have been investigated as seed-based approaches to overcome poor step coverage, while seedless strategies have also been proposed including additive-assisted electroplating, electroless alloy layers, metallic nanowires, and conductive pastes. These methods have demonstrated void-free or seam-free fills under specific conditions, yet challenges remain in achieving uniform superconformal filling across dense arrays, suppressing copper oxidation and interfacial contamination during rinsing/drying, and guaranteeing long-term reliability under thermomechanical cycling, electromigration, and humidity bias. In parallel, hybrid bonding has emerged as an alternative to thermo-compression bonding, where TSV filling performance, CMP (chemical mechanical polishing) planarization, and interface activation are crucial to reliable bonding. An integrated research approach incorporating both seed- and seedless-based TSV filling together with hybrid bonding provides a credible pathway to reliable three-dimensional stacking for high-bandwidth memory and artificial intelligence applications.
1. 서 론
2. TSV 시드층의 기술 동향
3. Seedless TSV 내 금속 충전 기술의 접근 방식
3.1. 첨가제 제어에 의한 TSV 내 Cu 전해도금: seed와seedless 금속 충전
3.2. 배리어/시드층을 겸하는 Seedless TSV 내 금속충전 기술
3.3. 금속 나노와이어 및 페이스트를 이용한 seedlessTSV 내 금속 충전 기술
3.4. Seedless TSV 내 금속 충전 기술의 한계
4. TSV 내 도금 공정 기술과 하이브리드 본딩법의연계 가능성
5. 결 론
Acknowledgement
References
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