Through-silicon via (TSV) filling is indispensable for three-dimensional semiconductor packaging. Conventional processes rely on PVD (physical vapor deposition) or ALD (atomic layer deposition) seed layer deposition followed by copper electroplating, but these approaches face limitations in productivity and conformality. ALD and ELD (electroless deposition) have been investigated as seed-based approaches to overcome poor step coverage, while seedless strategies have also been proposed including additive-assisted electroplating, electroless alloy layers, metallic nanowires, and conductive pastes. These methods have demonstrated void-free or seam-free fills under specific conditions, yet challenges remain in achieving uniform superconformal filling across dense arrays, suppressing copper oxidation and interfacial contamination during rinsing/drying, and guaranteeing long-term reliability under thermomechanical cycling, electromigration, and humidity bias. In parallel, hybrid bonding has emerged as an alternative to thermo-compression bonding, where TSV filling performance, CMP (chemical mechanical polishing) planarization, and interface activation are crucial to reliable bonding. An integrated research approach incorporating both seed- and seedless-based TSV filling together with hybrid bonding provides a credible pathway to reliable three-dimensional stacking for high-bandwidth memory and artificial intelligence applications.

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.