To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

A variety of statistical methods are applied to model and optimize responses, related to product or system's quality, in terms of control and noise factors at design and manufacturing stages. Most of them assume continuous response variables but, assessin

RAM(Reliability, Availability, Maintainability) is important performance factor to keep combat readiness and optimize operational and maintenance cost of weapon systems. This paper discusses the method to establish RAM for combat readiness by using field

A number of trend test methods, i.e., Military Handbook test and Laplace test etc., have been applied to investigate recurrent failures trend in repairable systems. Existing methods provide information about only existence of trend in the system. In this

신뢰성 평가 시험은 종종 성능 평가에 장기간의 시간이 요구되며, 전체 생산비용까지 증가시키는 문제점을 안고 있다. 스트레스를 이용한 가속수명시험은 제품의 신뢰성 고장과 밀접한 관련이 있는 고장 메커니즘의 촉진을 통해 고장에 이르는 기간을 단축함으로써 신뢰성 평가의 효율성을 도모할 수 있다. 본 연구에서는 이러한 스트레스 가속 시험에 빈도가속(Usage-Rate Acceleration) 또는 판정가속(Tightening Critical-Values) 등을

The need for accurate yield prediction is increasing for estimating productivity and production costs to secure high revenues in the semiconductor industry. Corresponding to this end, we introduce new spatial modeling approaches for spatially clustered defects on an integrated circuit (IC) wafer map. We use spatial location of an IC chip on the wafer as a covariate on corresponding defects count listed in a wafer map. Analysis results indicate that yield prediction can be greatly improved by capturing spatial features of defects. Tyagi and Bayoumi's (1994) wafer map data are used to illustrate the procedure.