Graphene has shown exceptional properties for high performance devices due to its high carrier mobility. Of particular interest is the potential use of graphene nanoribbons as field-effect transistors. Herein, we introduce a facile approach to the fabrication of graphene nanoribbon (GNR) arrays with ~200 nm width using nanoimprint lithography (NIL), which is a simple and robust method for patterning with high fidelity over a large area. To realize a 2D material-based device, we integrated the graphene nanoribbon arrays in field effect transistors (GNR-FETs) using conventional lithography and metallization on highly-doped Si/SiO2 substrate. Consequently, we observed an enhancement of the performance of the GNRtransistors compared to that of the micro-ribbon graphene transistors. Besides this, using a transfer printing process on a flexible polymeric substrate, we demonstrated graphene-silicon junction structures that use CVD grown graphene as flexible electrodes for Si based transistors.

Nanofabrication is an essential process throughout industry. Technologies that produce general nanofabrication, such as e-beam lithography, dip-pen lithography, DUV lithography, immersion lithography, and laser interference lithography, have drawbacks including complicated processes, low throughput, and high costs, whereas nano-transfer printing (nTP) is inexpensive, simple, and can produce patterns on non-plane substrates and multilayer structures. In general nTP, the coherency of gold-deposited stamps is strengthened by using SAM treatment on substrates, so the gold patterns are transferred from stamps to substrates. However, it is hard to apply to transfer other metallic materials, and the existing nTP process requires a complicated surface treatment. Therefore, it is necessary to simplify the nTP technology to obtain an easy and simple method for fabricating metal patterns. In this paper, asnTP process with poly vinyl alcohol (PVA) mold was proposed without any chemical treatment. At first, a PVA mold was duplicated from the master mold. Then, a Mo layer, with a thickness of 20 nm, was deposited on the PVA mold. The Mo deposited PVA mold was put on the Si wafer substrate, and nTP process progressed. After the nTP process, the PVA mold was removed using DI water, and transferred Mo nano patterns were characterized by a Scanning electron micrograph (SEM) and Energy Dispersive spectroscopy (EDS).