The design of a memory control chip is described which is intended for embedded operation in VLSI Chip for 3D image application. It consists of two SRAMs and memory controller. The two memories section and their address counters are being swapped from the storage to the call clock. The systems offers improved accuracy, repeatability, portability, and flexibility not available in current commercial systems. To reduced a chip, 4T(4 transistors) SRAM cells are used instead of the standard SRAM cells 6T (6 transistors) by which the leakage current is drastically reduced and low power is achieved. The layout of the memory chip is realized using Electric layout editor, the DRC and LVS is verified using Electric and post layout simulated with LT SPICE tool of computer.

Abstract
 1. 서론
 2. 데이터 획득 시스템의 구조와 동작
  2.1 SRAM의 구조
  2.2 주소 카운터
  2.3 메모리제어기
 3. 제안된 시스템 회로설계와 시뮬레이션
  3.1 SRAM 셀 회로 시뮬레이션
  3.2 센스 앰프 시뮬레이션
  3.3 주소카운터 시뮬레이션
  3.4 메모리 제어 시스템 시뮬레이션
  3.5 레이아웃
 4. 결론
 참고문헌

• 권승탁(서남대학교 컴퓨터정보통신학과) | Seungtag Kwon
• 이계철(군장대학 자동차기계계열) | Kyecheul Lee