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        검색결과 4

        1.
        2015.06 KCI 등재 구독 인증기관 무료, 개인회원 유료
        In this paper we describe differential circuit of charge pump for voltage management systems, their evolution and improvement in design. The systems are powered by solar cells and generate different voltage levels which are suitable for systems on-chip integrated regulator applications. The voltage regulator outputs voltage from low power digital circuit, -2V for memory, and from 2V to 12V for input and output components. The circuits were simulated using LT SPICE software.
        3,000원
        2.
        2013.12 KCI 등재 구독 인증기관 무료, 개인회원 유료
        In this paper, we present a CMOS voltage regulator for application in electric device. This works shows that unlike the traditional voltage converter, this regulator can achieve high efficiency with a good step-down voltage ratio. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.
        4,000원
        3.
        2013.08 KCI 등재 구독 인증기관 무료, 개인회원 유료
        The paper describes variable circuits technique the enable of differential circuit of charge pump. It is able to pump an input voltage of 2V to measure several output voltage through several clock signal with each pumping capacitor of 1 pF and smoothing capacitor of 1 pF at the output. From the simulation result, it is evident that charge pump circuits offer verity high voltage pumping gain. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.
        4,000원
        4.
        2010.09 KCI 등재 구독 인증기관 무료, 개인회원 유료
        The design of a memory control chip is described which is intended for embedded operation in VLSI Chip for 3D image application. It consists of two SRAMs and memory controller. The two memories section and their address counters are being swapped from the storage to the call clock. The systems offers improved accuracy, repeatability, portability, and flexibility not available in current commercial systems. To reduced a chip, 4T(4 transistors) SRAM cells are used instead of the standard SRAM cells 6T (6 transistors) by which the leakage current is drastically reduced and low power is achieved. The layout of the memory chip is realized using Electric layout editor, the DRC and LVS is verified using Electric and post layout simulated with LT SPICE tool of computer.
        4,000원