Recently, the demand for the miniaturization of package substrates has been increasing. Technical innovation has occurred to move package substrate manufacturing steps into CMP applications. Electroplated copper filled trenches on the substrate need to be planarized for multi-level wires of less than 10μm. This paper introduces a chemical mechanical planarization (CMP) process as a new package substrate manufacturing step. The purpose of this study is to investigate the effect of surfactant on the dishing and erosion of Cu patterns with the lines and spaces of around 10/10μm used for advanced package substrates. The use of a conventional Cu slurry without surfactant led to problems, including severe erosion of 0.58μm in Cu patterns smaller than 4/6μm and deep dishing of 4.2μm in Cu patterns larger than 14/16μm. However, experimental results showed that the friction force during Cu CMP changed to lower value, and that dishing and erosion became smaller simultaneously as the surfactant concentration became higher. Finally, it was possible to realize more globally planarized Cu patterns with erosion ranges of 0.22μm to 0.35μm and dishing ranges of 0.37μm to 0.69μm by using 3 wt% concentration of surfactant.

실리콘 웨이퍼 직접 접합을 성공하기 위해서는 양호한 접합면을 구성하여야 하며, 이를 위해 접합면에서 발생하는 주요 결함 중 하나인 기포형 접합 결함을 억제하여야 한다. 본 연구에서는 접합면에서 발생하는 기포형 결함의 상온 접합 및 열처리 과정에서의 거동을 관찰하여 내부의 압력이 증가함을 직접 관찰할 수 있었다. 또한, 대기압 하의 열처리에서 결함이 발생하지 않는 SiO2-SiO2 접합 웨이퍼가 진공에서의 열처리에서 결함이 발생하는 현상을 통해 기포형 결함의 내부 압력과 성장과의 관계를 실험을 통하여 증명할 수 있었다.