In crystalline solar cells, the substrate itself constitutes a large portion of the fabrication cost as it is derived fromsemiconductor ingots grown in costly high temperature processes. Thinner wafer substrates allow some cost saving as morewafers can be sliced from a given ingot, although technological limitations in slicing or sawing of wafers off an ingot, as wellas the physical strength of the sliced wafers, put a lower limit on the substrate thickness. Complementary to these economicaland techno-physical points of view, a device operation point of view of the substrate thickness would be useful. With this inmind, BC-BJ Si and GaAs solar cells are compared one to one by means of the Medici device simulation, with a particularemphasis on the substrate thickness. Under ideal conditions of 0.6µm photons entering the 10µm-wide BC-BJ solar cells atthe normal incident angle (θ=90o), GaAs is about 2.3 times more efficient than Si in terms of peak cell power output:42.3mW·cm−2 vs. 18.2mW·cm−2. This strong performance of GaAs, though only under ideal conditions, gives a strongindication that this material could stand competitively against Si, despite its known high material and process costs. Within thelimitation of the minority carrier recombination lifetime value of 5×10−5 sec used in the device simulation, the solar cell poweris known to be only weakly dependent on the substrate thickness, particularly under about 100µm, for both Si and GaAs.Though the optimum substrate thickness is about 100µm or less, the reduction in the power output is less than 10% from thepeak values even when the substrate thickness is increased to 190µm. Thus, for crystalline Si and GaAs with a relatively longrecombination lifetime, extra efforts to be spent on thinning the substrate should be weighed against the expected actual gainin the solar cell output power.

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and thechannel depth (D) at 3:1 or larger is known to be critical in preventing deleterious short-channel effects. Inthis study, n-type SOI-MOSFETs with a channel length of 0.1µm and a Si film thickness (channel depth) of0.033µm (L:D=3:1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioningtransistors on the very thin Si film, a protective layer of 0.08µm-thick surface oxide was deposited prior tothe source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron dopingconcentration of the Si film, in which the device channel is formed, was used as the key variable in the processsimulation. The finished devices were electrically tested with a Medici device simulator. The result showedthat, for a given channel doping concentration of 1.9~2.5×1018cm−3, the threshold voltage was 0.5~0.7V, andthe subthreshold swing was 70~80mV/dec. These value ranges are all fairly reasonable and should form a‘magic region’ in which SOI-MOSFETs run optimally.