This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

1시간 주기로 -35˚C에서 +125˚C까지의 온도 변화에 지배되는 Leadless Ceranic Chip Carriers(LLCC'S)의 Solder접합부에서 균열이 계면을 따라 일어났다. 이런 균열이 계면을 취약하게 하는 어떤 불순물에 의한 것이 아닌지를 Scanning Auger Microprobe(SAM)을 이용해 조사했다. 그 결과 계면을 따라 일어나는 균열이 계면의 산화에 의해 일어날 수 있다는 것이 발견되었고, 그에 따라 산화에 취약해진 계면을 따라 일어나는 이런 종류의 피로 파괴현상에 대한 모델을 제시했다.