This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

탄성 반도체 칩과 점탄성 접착제층의 계면에 존재하는 모서리 균열에 대한 응력확대계수를 조사하였다. 이러한 균열들은 자유 경계면 부근에 존재하는 응력 특이성으로 인해 발생할 수 있다. 계면 응력상태를 해석하기 위해서 시간 영역 경계요소법이 사용되었다. 작은 크기의 모서리 균열에 대한 응력확대계수가 계산되었다. 점탄성 이완으로 인해 응력확대계수의 크기는 시간이 경과함에 따라 작아진다.