In this study, a new manufacturing process for a multilayer-clad electrical contact material is suggested. A thin and dense BCuP-5 (Cu-15Ag-5P filler metal) coating layer is fabricated on a Ag plate using a high-velocity oxygen-fuel (HVOF) process. Subsequently, the microstructure and bonding properties of the HVOF BCuP-5 coating layer are evaluated. The thickness of the HVOF BCuP-5 coating layer is determined as 34.8 μm, and the surface fluctuation is measured as approximately 3.2 μm. The microstructure of the coating layer is composed of Cu, Ag, and Cu-Ag-Cu3P ternary eutectic phases, similar to the initial BCuP-5 powder feedstock. The average hardness of the coating layer is 154.6 HV, which is confirmed to be higher than that of the conventional BCuP-5 alloy. The pull-off strength of the Ag/BCup-5 layer is determined as 21.6 MPa. Thus, the possibility of manufacturing a multilayer-clad electrical contact material using the HVOF process is also discussed.

A multi-step deposition process for the gap-filling of submicrometer trenches using dimethyldimethoxysilane (DMDMOS), (CH3)2Si(OCH3)2, and CxHyOz by plasma enhanced chemical vapor deposition (PECVD) is presented. The multistep process consisted of pre-treatment, deposition, and post-treatment in each deposition step. We obtained low-k films with superior gap-filling properties on the trench patterns without voids or delamination. The newly developed technique for the gapfilling of submicrometer features will have a great impact on inter metal dielectric (IMD) and shallow trench isolation (STI) processes for the next generation of microelectronic devices. Moreover, this bottom up gap-fill mode is expected to be universally for other chemical vapor deposition systems.

3-D IC integration enables the smallest form factor and highest performance due to the shortest and most plentiful interconnects between chips. Direct metal bonding has several advantages over the solder-based bonding, including lower electrical resistivity, better electromigration resistance and more reduced interconnect RC delay, while high process temperature is one of the major bottlenecks of metal direct bonding because it can negatively influence device reliability and manufacturing yield. We performed quantitative analyses of the interfacial properties of Al-Al bonds with varying process parameters, bonding temperature, bonding time, and bonding environment. A 4-point bending method was used to measure the interfacial adhesion energy. The quantitative interfacial adhesion energy measured by a 4-point bending test shows 1.33, 2.25, and 6.44 J/m2 for 400, 450, and 500˚C, respectively, in a N2 atmosphere. Increasing the bonding time from 1 to 4 hrs enhanced the interfacial fracture toughness while the effects of forming gas were negligible, which were correlated to the bonding interface analysis results. XPS depth analysis results on the delaminated interfaces showed that the relative area fraction of aluminum oxide to the pure aluminum phase near the bonding surfaces match well the variations of interfacial adhesion energies with bonding process conditions.

This paper describes an improved strategy for controlling the adhesion force using both the antiadhesion and adhesion layers for a successful large-area transfer process. An MPTMS (3-mercaptopropyltrimethoxysilane) monolayer as an adhesion layer for Au/Pd thin films was deposited on Si substrates by vapor self assembly monolayer (VSAM) method. Contact angle, surface energy, film thickness, friction force, and roughness were considered for finding the optimized conditions. The sputtered Au/Pd (~17 nm) layer on the PDMS stamp without the anti-adhesion layer showed poor transfer results due to the high adhesion between sputtered Au/Pd and PDMS. In order to reduce the adhesion between Au/Pd and PDMS, an anti-adhesion monolayer was coated on the PDMS stamp using FOTS (perfluorooctyltrichlorosilane) after O2 plasma treatment. The transfer process with the anti-adhesion layer gave good transfer results over a large area (20 mm × 20 mm) without pattern loss or distortion. To investigate the applied pressure effect, the PDMS stamp was sandwiched after 90˚ rotation on the MPTMS-coated patterned Si substrate with 1-μm depth. The sputtered Au/Pd was transferred onto the contact area, making square metal patterns on the top of the patterned Si structures. Applying low pressure helped to remove voids and to make conformal contact; however, high pressure yielded irregular transfer results due to PDMS stamp deformation. One of key parameters to success of this transfer process is the controllability of the adhesion force between the stamp and the target substrate. This technique offers high reliability during the transfer process, which suggests a potential building method for future functional structures.

이 논문에서는, 반도체 칩과 리드프레임을 결합하는 과정에서 점탄성 접착제층에 발생하는 잔류응력 문제를 다루고 있다. 접착제층은 열유동단순거동을 한다고 가정하였다. 접착제층에서의 응력들은 경계요소법을 사용하여 조사하였다. 매우 큰 응력 구배가 계면 모서리에서 발생하는데, 그러한 응력들은 국부 항복을 일으키거나, 칩과 리드프레임의 박리를 야기시킬 수 있음을 보여주고 있다.