We report a simple procedure to fabricate single crystals 3D C60 having an FCC structure on silicon substrates using a vapour–solid set-up in vacuum conditions. The morphology of the deposited film can be tuned by controlling the temperature and position of the substrate. The as-fabricated samples are extensively characterised by transmission electron microscopy, scanning electron microscope, X-ray powder diffraction, Raman spectroscopy, X-ray photoelectron spectroscopy and nanoindentation, which allow us to shed light on the recrystallization process of the C60. In addition, the growth mechanism of the formation of crystalline 3D structure of the C60 film is discussed in detail. Based on the newly gained knowledge of mechanism and its unique properties, fullerene has shown huge potential as a solid lubricant on various kinds of substrates.

Recently, research on cost reduction and efficiency improvement of crystalline silicon(c-Si) photovoltaic(PV) module has been conducted. In order to reduce costs, the thickness of solar cell wafers is becoming thinner. If the thickness of the wafer is reduced, cracking of wafer may occur in high temperature processes during the c-Si PV module manufacturing process. To solve this problem, a low temperature process has been proposed. Conductive paste(CP) is used for low temperature processing; it contains Sn57.6Bi0.4Ag component and can be electrically combined with solar cells and ribbons at a melting point of 150℃. Use of CP in the PV module manufacturing process can minimize cracks of solar cells. When CP is applied to solar cells, the output varies with the amount of CP, and so the optimum amount of CP must be found. In this paper, in order to find the optimal CP application amount, we manufactured several c-Si PV modules with different CP amounts. The amount control of CP is fixed at air pressure (500 kPa) and nozzle diameter 22G(outer diameter 0.72Ø, inner 0.42Ø) of dispenser; only speed is controlled. The c-Si PV module output is measured to analyze the difference according to the amount of CP and analyzed by optical microscope and Alpha-step. As the result, the optimum amount of CP is 0.452 ~ 0.544 g on solar cells.

In this study, using a wet chemical process, we evaluate the effectiveness of different solution concentrations in removing layers from a solar cell, which is necessary for recovery of high-purity silicon . A 4-step wet etching process is applied to a 6-inch back surface field(BSF) solar cell. The metal electrode is removed in the first and second steps of the process, and the anti-reflection coating(ARC) is removed in the third step. In the fourth step, high purity silicon is recovered by simultaneously removing the emitter and the BSF layer from the solar cell. It is confirmed by inductively coupled plasma mass spectroscopy(ICP-MS) and secondary ion mass spectroscopy(SIMS) analyses that the effectiveness of layer removal increases with increasing chemical concentrations. The purity of silicon recovered through the process, using the optimal concentration for each process, is analyzed using inductively coupled plasma atomic emission spectroscopy(ICP-AES). In addition, the silicon wafer is recovered through optimum etching conditions for silicon recovery, and the solar cell is remanufactured using this recovered silicon wafer. The efficiency of the remanufactured solar cell is very similar to that of a commercial wafer-based solar cell, and sufficient for use in the PV industry.

In recent years, solar cells based on crystalline silicon(c-Si) have accounted for much of the photovoltaic industry. The recent studies have focused on fabricating c-Si solar modules with low cost and improved efficiency. Among many suggested methods, a photovoltaic module with a shingled structure that is connected to a small cut cell in series is a recent strong candidate for low-cost, high efficiency energy harvesting systems. The shingled structure increases the efficiency compared to the module with 6 inch full cells by minimizing optical and electrical losses. In this study, we propoese a new Conductive Paste (CP) to interconnect cells in a shingled module and compare it with the Electrical Conductive Adhesives (ECA) in the conventional module. Since the CP consists of a compound of tin and bismuth, the module is more economical than the module with ECA, which contains silver. Moreover, the melting point of CP is below 150 ℃, so the cells can be integrated with decreased thermal-mechanical stress. The output of the shingled PV module connected by CP is the same as that of the module with ECA. In addition, electroluminescence (EL) analysis indicates that the introduction of CP does not provoke additional cracks. Furthermore, the CP soldering connects cells without increasing ohmic losses. Thus, this study confirms that interconnection with CP can integrate cells with reduced cost in shingled c-Si PV modules.

In commercial solar cells, the pattern of the front electrode is critical to effectively assemble the photo generated current. The power loss in solar cells caused by the front electrode was categorized as four types. First, losses due to the metallic resistance of the electrode. Second, losses due to the contact resistance of the electrode and emitter. Third, losses due to the emitter resistance when current flows through the emitter. Fourth, losses due to the shading effect of the front metal electrode, which has a high reflectance. In this paper, optimizing the number of finger on a 4 ´ 4 solar cell is demonstrated with known theory. We compared the short circuit current density and fill factor to evaluate the power loss from the front metal contact calculation result. By experiment, the short circuit current density(Jsc), taken in each pattern as 37.61, 37.53, and 37.38 mA/ cm2 decreased as the number of fingers increased. The fill factor(FF), measured in each pattern as 0.7745, 0.7782 and 0.7843 increased as number of fingers increased. The results suggested that the efficiency(Eff) was measured in each pattern as 17.51, 17.81, and 17.84 %. Throughout this study, the short-circuit current densities(Jsc) and fill factor(FF) varied according to the number of fingers in the front metal pattern. The effects on the efficiency of the two factors were also investigated.

Reactive Ion Etching (RIE) and wet etching are employed in existing texturing processes to fabricate solar cells. Laser etching is used for particular purposes such as selective etching for grooves. However, such processes require a higher level of cost and longer processing time and those factors affect the unit cost of each process of fabricating solar cells. As a way to reduce the unit cost of this process of making solar cells, an atmospheric plasma source will be employed in this study for the texturing of crystalline silicon wafers. In this study, we produced the atmospheric plasma source and examined its basic properties. Then, using the prepared atmospheric plasma source, we performed the texturing process of crystalline silicon wafers. The results obtained from texturing processes employing the atmospheric plasma source and employing RIE were examined and compared with each other. The average reflectance of the specimens obtained from the atmospheric plasma texturing process was 7.88 %, while that of specimens obtained from the texturing process employing RIE was 8.04 %. Surface morphologies of textured wafers were examined and measured through Scanning Electron Microscopy (SEM) and similar shapes of reactive ion etched wafers were found. The Power Conversion Efficiencies (PCE) of the solar cells manufactured through each process were 16.97 % (atmospheric plasma texturing) and 16.29% (RIE texturing).

With the increase in installed solar energy capacity, comparison and analysis of the physical property values of solar cells are becoming increasingly important for production. Therefore, research on determining the physical characteristic values of solar cells is being actively pursued. In this study, a diode equation, which is commonly used to describe the I-V behavior and determine the electrical characteristic values of solar cells, was applied. Using this method, it is possible to determine the diode ideality factor (n) and series resistance (Rs) based on light I-V measurements. Thus, using a commercial screen-printed solar cell and an interdigitated back-contact solar cell, we determined the ideality factor (n) and series resistance (Rs) with a modified diode equation method for the light I-V curves. We also used the sun-shade method to determine the ideality factor (n) and series resistance (Rs) of the samples. The values determined using the two methods were similar. However, given the error in the sun-shade method, the diode equation is considered more useful than the sun-shade method for analyzing the electrical characteristics because it determines the ideality factor (n) and series resistance (Rs) based on the light I-V curves.

This paper presents the impact of partial shading on CuInxGa(1-x)Se2(CIGS) photovoltaic(PV) modules with bypass diodes. When the CIGS PV modules were partially shaded, the modules were under conditions of partial reverse bias. We investigated the characterization of the bypass diode and solar cell properties of the CIGS PV modules when these was partially shaded, comparing the results with those for a crystalline silicon module. In crystalline silicon modules, the bypass diode was operated at a partial shade modules of 1.67 % shading. This protected the crystalline silicon module from hot spot damage. In CIGS thin film modules, on the other hand, the bypass diode was not operated before 20 % shading. This caused damage because of hotspots, which occurred as wormlike defects in the CIGS thin film module. Moreover, the bypass diode adapted to the CIGS thin film module was operated fully at 60% shading, while the CIGS thin film module was not operated under these conditions. It is known that the bypass diode adapted to the CIGS thin film module operated more slowly than that of the crystalline silicon module; this bypass diode also failed to protect the module from damage. This was because of the reverse saturation current of the CIGS thin film, 1.99 × 10−5 A/cm2, which was higher than that of crystalline silicon, 8.11 × 10−7 A/cm2.

Solar cells exhibit different power outputs in different climates. In this study, the temperature dependence of open-circuit voltage(V-oc), short-circuit current(I-sc), fill factor(FF) and the efficiency of screen-printed single-crystal silicon solar cells were studied. One group was fabricated with homogeneously-doped emitters and another group was fabricated with selectively-doped emitters. While varying the temperature (25, 40, 60 and 80˚C), the current-voltage characteristics of the cells were measured and the leakage currents extracted from the current-voltage curve. As the temperature increased, both the homogeneously-doped and selectively-doped emitters showed a slight increase in I-sc and a rapid degradation of V-oc. The FF and efficiency also decreased as temperature increased in both groups. The temperature coefficient for each factor was calculated. From the current-voltage curve, we found that the main cause of V-oc degradation was an increase in the intrinsic carrier concentration. The temperature coefficients of the two groups were compared, leading to the idea that structural effects could also affect the temperature dependence of current-voltage characteristics.

The use of solar energy generation is steadily increasing, and photovoltaic modules are connected in series to generate higher voltage and power. However, solar panels are exposed to high-voltage stress (up to several hundreds of volts) between grounded module frames and the solar cells. Frequent high-voltage stress causes a power-drop in the modules, and this kind of degradation is called potential induced degradation (PID). Due to PID, a significant loss of power and performance has been reported in recent years. Many groups have suggested how to prevent or reduce PID, and have tried to determine the origin and mechanism of PID. Even so, the mechanism of PID is still unclear. This paper is focused on understanding the PID of crystalline-silicon solar cells and modules. A background for PID, as well as overviews of research on factors accelerating PID, mechanisms involving sodium ions, PID test methods, and possible solutions to the problem of PID, are covered in this paper.

To reduce manufacturing costs of crystalline silicon solar cells, silicon wafers have become thinner. In relation to this, the properties of the aluminium-back surface field (Al-BSF) are considered an important factor in solar cell performance. Generally, screen-printing and a rapid thermal process (RTP) are utilized together to form the Al-BSF. This study evaluates Al-BSF formation on a (111) textured back surface compared with a (100) flat back surface with variation of ramp up rates from 18 to 89˚C/s for the RTP annealing conditions. To make different back surface morphologies, one side texturing using a silicon nitride film and double side texturing were carried out. After aluminium screen-printing, Al-BSF formed according to the RTP annealing conditions. A metal etching process in hydrochloric acid solution was carried out to assess the quality of Al-BSF. Saturation currents were calculated by using quasi-steady-state photoconductance. The surface morphologies observed by scanning electron microscopy and a non-contacting optical profiler. Also, sheet resistances and bulk carrier concentration were measured by a 4-point probe and hall measurement system. From the results, a faster ramp up during Al-BSF formation yielded better quality than a slower ramp up process due to temperature uniformity of silicon and the aluminium surface. Also, in the Al-BSF formation process, the (111) textured back surface is significantly affected by the ramp up rates compared with the (100) flat back surface.

In this paper, double texturization of multi crystalline silicon solar cells was studied with laser and reactive ion etching (RIE). In the case of multi crystalline silicon wafers, chemical etching has problems in producing a uniform surface texture. Thus various etching methods such as laser and dry texturization have been studied for multi crystalline silicon wafers. In this study, laser texturization with an Nd:YVO4 green laser was performed first to get the proper hole spacing and 300μm was found to be the most proper value. Laser texturization on crystalline silicon wafers was followed by damage removal in acid solution and RIE to achieve double texturization. This study showed that double texturization on multi crystalline silicon wafers with laser firing and RIE resulted in lower reflectance, higher quantum yield and better efficiency than that process without RIE. However, RIE formed sharp structures on the silicon wafer surfaces, which resulted in 0.8% decrease of fill factor at solar cell characterization. While chemical etching makes it difficult to obtain a uniform surface texture for multi crystalline silicon solar cells, the process of double texturization with laser and RIE yields a uniform surface structure, diminished reflectance, and improved efficiency. This finding lays the foundation for the study of low-cost, high efficiency multi crystalline silicon solar cells.

The simulation program for solar cells, PC1D, was briefly reviewed and the device modeling of a multicrystalline Si solar cell using the program was carried out to understand the internal operating principles. The effects of design parameters on the light absorption and the quantum efficiency were investigated and strategies to reduce carrier recombination, such as back surface field and surface passivation, were also characterized with the numerical simulation. In every step of the process, efficiency improvements for the key performance characteristics of the model device were determined and compared with the properties of the solar cell, whose efficiency (20.3%) has been confirmed as the highest in multicrystalline Si devices. In this simulation work, it was found that the conversion efficiency of the prototype model (13.6%) can be increased up to 20.7% after the optimization of design parameters.