As the demand for p-type semiconductors increases, much effort is being put into developing new p-type materials. This demand has led to the development of novel new p-type semiconductors that go beyond existing p-type semiconductors. Copper iodide (CuI) has recently received much attention due to its wide band gap, excellent optical and electrical properties, and low temperature synthesis. However, there are limits to its use as a semiconductor material for thin film transistor devices due to the uncontrolled generation of copper vacancies and excessive hole doping. In this work, p-type CuI semiconductors were fabricated using the chemical vapor deposition (CVD) process for thin-film transistor (TFT) applications. The vacuum process has advantages over conventional solution processes, including conformal coating, large area uniformity, easy thickness control and so on. CuI thin films were fabricated at various deposition temperatures from 150 to 250 °C The surface roughness root mean square (RMS) value, which is related to carrier transport, decreases with increasing deposition temperature. Hall effect measurements showed that all fabricated CuI films had p-type behavior and that the Hall mobility decreased with increasing deposition temperature. The CuI TFTs showed no clear on/off because of the high concentration of carriers. By adopting a Zn capping layer, carrier concentrations decreased, leading to clear on and off behavior. Finally, stability tests of the PBS and NBS showed a threshold voltage shift within ±1 V.

휘어지며 투명한 전자기기의 개발을 위해서 최근 유기반도체, 탄소기반 나노소재, 금속산화물 반도체등의 다양한 신소재 반도체 개발에 대한 연구가 관심을 받으며 지속적으로 발전하고 있다. 그러나, 이러한 신소재 반도체 기술의 꾸준하고 지속적인 발전에도 불구하고 트랜지스터를 구성하는 주요 소재중 하나인 유전체에 대한 연구는 반도체의 개발속도에 크게 미치지 못하여, 기계적인 휘어짐의 특성을 갖추고, 높은 캐패시턴스와 좋은 누전전류 특성을 갖는 새로운 유전체 개발에 대한 요구가 지속적으로 커지고 있다. 이에 본 연구는 저전압에서 구동 가능한 박막트랜지스터를 위한 유기-무기 하이브리드소재 박막을 개발하며 이를 저전압 구동이 가능한 유기박막트랜지스터에 적용하였다. 상대적으로 높은 유전상수를 갖는 염화하프늄 (HfO2)과 소수성기를 갖고 있으며 금속산화물과 공유결합이 가능한 실란산 기반의 유기물 (octadecyltrimethoxysilane)을 혼합한 전구체 용액을 합성하며 상대적으로 낮은 온도에서 열처리를 통해 얻을 수 있었다. 제조된 하이브리드 게이트 유전체 박막은 우수한 절연 및 유전체 특성과 함께 소수성 표면 특성을 가질 수 있었고 펜타센 유기박막트랜지스터로 응용하여 저전압에서 구동이 되며 우수한 트랜지스터 성능을 갖는 소자를 개발하였다.

Oxide semiconductor, represented by a-IGZO, has been commercialized in the market as active layer of TFTs of display backplanes due to its various advantages over a-Si. a-IGZO can be deposited at room temperature by RF magnetron sputtering process; however, additional thermal annealing above 300oC is required to obtain good semiconducting properties and stability. These temperature are too high for common flexible substrates like PET, PEN, and PI. In this work, effects of microwave annealing time on IGZO thin film and associated thin-film transistors are demonstrated. As the microwave annealing time increases, the electrical properties of a-IGZO TFT improve to a degree similar to that during thermal annealing. Optimal microwave annealed IGZO TFT exhibits mobility, SS, Vth, and VH of 6.45 cm2/Vs, 0.17 V/dec, 1.53 V, and 0.47 V, respectively. PBS and NBS stability tests confirm that microwave annealing can effectively improve the interface between the dielectric and the active layer.

Amorphous In-Ga-Zn-O (a-IGZO) thin film transistors, because of their relatively low mobility, have limits in attempts to fulfill high-end specifications for display backplanes. In-Zn-O (IZO) is a promising semiconductor material for high mobility device applications with excellent transparency to visible light region and low temperature process capability. In this paper, the effects of working pressure on the physical and electrical properties of IZO films and thin film transistors are investigated. The working pressure is modulated from 2 mTorr to 5 mTorr, whereas the other process conditions are fixed. As the working pressure increases, the extracted optical band gap of IZO films gradually decreases. Absorption coefficient spectra indicate that subgap states increase at high working pressure. Furthermore, IZO film fabricated at low working pressure shows smoother surface morphology. As a result, IZO thin film transistors with optimum conditions exhibit excellent switching characteristics with high mobility (≥ 30cm2/Vs) and large on/off ratio.

The effects of fast neutron irradiation on the electrical and optical properties of Li (3 at%) doped ZnSnO (ZTO) thin films fabricated using a sol-gel process are investigated. From the results of Li-ZTO TFT characteristics according to change of neutron irradiation time, the saturation mobility is found to increase and threshold voltage values shift to a negative direction from 1,000 s neutron irradiation time. X-ray photoelectron spectroscopy analysis of the O 1s core level shows that the relative area of oxygen vacancies is almost unchanged with different irradiation times. From the results of band alignment, it is confirmed that, due to the increase of electron carrier concentration, the Fermi level (EF) of the sample irradiated for 1,000 s is located at the position closest to the conduction band minimum. The increase in electron concentration is considered by looking at the shallow band edge state under the conduction band edge formed by fast neutron irradiation of more than 1,000 s.

We examined the characteristics of indium tin zinc oxide (ITZO) thin film transistors (TFTs) on polyimide (PI) substrates for next-generation flexible display application. In this study, the ITZO TFT was fabricated and analyzed with a SiOx/ SiNx gate insulator deposited using plasma enhanced chemical vapor deposition (PECVD) below 350℃. X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) results revealed that the oxygen vacancies and impurities such as H, OH and H2O increased at ITZO/gate insulator interface. Our study suggests that the hydrogen related impurities existing in the PI and gate insulator were diffused into the channel during the fabrication process. We demonstrate that these impurities and oxygen vacancies in the ITZO channel/gate insulator may cause degradation of the electrical characteristics and bias stability. Therefore, in order to realize high performance oxide TFTs for flexible displays, it is necessary to develop a buffer layer (e.g., Al2O3) that can sufficiently prevent the diffusion of impurities into the channel.

The effects of electron beam(EB) irradiation on the electrical and optical properties of InGaZnO(IGZO) thin films fabricated using a sol-gel process were investigated. As the EB dose increased, the electrical characteristic of the IGZO TFTs changed from semiconductor to conductor, and the threshold voltage values shifted to the negative direction. X-ray photoelectron spectroscopy analysis of the O 1s core level showed that the relative area of oxygen vacancies increased from 14.68 to 19.08 % as the EB dose increased from 0 to 1.5 × 1016 electrons/cm2. In addition, spectroscopic ellipsometer analysis showed that the optical band gap varied from 3.39 to 3.46 eV with increasing EB dose. From the result of band alignment, it was confirmed that the Fermi level(EF) of the sample irradiated with 1.5 × 1016 electrons/cm2 was located at the closest position to the conduction band minimum(CBM) due to the increase of electron carrier concentration

The effect of electron beam (EB) irradiation on the electrical properties of Zn-Sn-O (ZTO) thin films fabricated using a sol-gel process was investigated. As the EB dose increased, the saturation mobility of ZTO thin film transistors (TFTs) was found to slightly decrease, and the subthreshold swing and on/off ratio degenerated. X-ray photoelectron spectroscopy analysis of the O 1s core level showed that the relative area of oxygen vacancies (VO) increased from 10.35 to 12.56 % as the EB dose increased from 0 to 7.5 × 1016 electrons/cm2. Also, spectroscopic ellipsometry analysis showed that the optical band gap varied from 3.53 to 3.96 eV with increasing EB dose. From the results of the electrical property and XPS analyses of the ZTO TFTs, it was found that the electrical characteristic of the ZTO thin films changed from semiconductor to conductor with increasing EB dose. It is thought that the electrical property change is due to the formation of defect sites like oxygen vacancies.

We have investigated the properties of thin film transistors(TFT) fabricated using zinc tin oxide(ZTO) thin films deposited via on-axis sputtering and FTS methods. ZTO thin films deposited by FTS showed lower root-mean-square(RMS) roughness and more uniformity than those deposited via on-axis sputtering. We observed enhanced electrical properties of ZTO TFT deposited via FTS. The ZTO films were deposited at room temperature via on-axis sputtering and FTS. The as-deposited ZTO films were annealed at 400 oC. The TFT using the ZTO films deposited via FTS process exhibited a high mobility of 12.91 cm2/V.s, a low swing of 0.80 V/decade, Vth of 5.78 V, and a high Ion/off ratio of 2.52 × 106.

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide whichcan enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was thenprepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a NiCl2 environment. Afterremoving surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemicalvapor deposition at 200oC. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing(RTA) process at 730oC for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as thecrystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer wasepitaxially crystallized with the help of NiSi2 precipitates that originated from the poly-Si seed layer. The crystallinity of theSERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process.The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to 1×1018cm−3. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by theSERTA process were 85cm2/V·s and 1.23V/decade at Vds=−3V, respectively. The off current was little increased underreverse bias from 1.0×10−11 A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakagecurrent can be fabricated with more precise experiments.

To obtain the transistor with ambipolar transfer characteristics, IGZO/SiOC thin film transistor was prepared on SiOC with various polarities as a gate insulator. The interface between a channel and insulator showed the Ohmic and Schottky contacts in the bias field of -5V ~ +5V. These contact characteristics depended on the polarities of SiOC gate insulators. The transfer characteristics of TFTs were observed the Ohmic contact on SiOC with polarity, but Schottky contact on SiOC with low polarity. The IGZO/SiOC thin film transistor with a Schottky contact in a short range bias electric field exhibited ambipolar transfer characteristics, but that with Ohmic contact in a short range electric field showed unipolar characteristics by the trapping phenomenon due to the trapped ionized defect formation.

유기 박막 트랜지스터 (organic thin-film transistors; OTFTs)는 유기 반도체 그리고 디스플레이와 같은 분야에 그들의 잠재적인 응용 가능성 때문에 많은 주목을 받고 있다. 하지만 급격한 산화 혹은 낮은 전기 이동도와 같은 단점으로 인하여 n-형 물질은 p-형 물질에 비해서 상대적으로 많은 연구가 진행되지 못한 실정이다. 따라서 본 논문에서는 n-형 반도체 물질인 [6,6]-phenyl-C61-butyricacidmethylester (PCBM)과 Poly(4-vinylphenol) (PVP)을 유기 절연막으로 이용하여 o-dichlorobenzene, toluene and chloroform과 같은 다양한 유기 용매를 사용한 플라스틱 기판에 유기트랜지스터를 제작하였고 유기 용매가 ODCB 경우 전계 효과 이동도는 약 0.034 cm2/Vs 그리고 점멸비(on/off ratio)는 ~1.3×105 으로 향상 되었다. 다양한 유기 용매의 휘발성에 따라서 PCBM TFT의 전기적 특성에 미치는 영향을 규명하였다.

We studied the influence of different types of metal electrodes on the performance of solution-processed zinc tin oxide (ZTO) thin-film transistors. The ZTO thin-film was obtained by spin-coating the sol-gel solution made from zinc acetate and tin acetate dissolved in 2-methoxyethanol. Various metals, Al, Au, Ag and Cu, were used to make contacts with the solution-deposited ZTO layers by selective deposition through a metal shadow mask. Contact resistance between the metal electrode and the semiconductor was obtained by a transmission line method (TLM). The device based on an Al electrode exhibited superior performance as compared to those based on other metals. Kelvin probe force microscopy (KPFM) allowed us to measure the work function of the oxide semiconductor to understand the variation of the device performance as a function of the types metal electrode. The solution-processed ZTO contained nanopores that resulted from the burnout of the organic species during the annealing. This different surface structure associated with the solution-processed ZTO gave a rise to a different work function value as compared to the vacuum-deposited counterpart. More oxygen could be adsorbed on the nanoporous solution-processed ZTO with large accessible surface areas, which increased its work function. This observation explained why the solution-processed ZTO makes an ohmic contact with the Al electrode.

Oxide semiconductors Thin-film transistors are an exemplified one owing to its excellent ambient stability and optical transparency. In particular zinc oxide (ZnO) has been reported because It has stability in air, a high electron mobility, transparency and low light sensitivity, compared to any other materials. For this reasons, ZnO TFTs have been studied actively. Furthermore, we expected that would be satisfy the demands of flexible display in new generation. In order to do that, ZnO TFTs must be fabricated that flexible substrate can sustain operating temperature. So, In this paper we have studied low-temperature process of zinc oxide(ZnO) thin-film transistors (TFTs) based on silicon nitride (SiNx)/cross-linked poly-vinylphenol (C-PVP) as gate dielectric. TFTs based on oxide fabricated by Low-temperature process were similar to electrical characteristics in comparison to conventional TFTs. These results were in comparison to device with SiNx/low-temperature C-PVP or SiNx/conventional C-PVP. The ZnO TFTs fabricated by low-temperature process exhibited a field-effect mobility of 0.205 cm2/Vs, a thresholdvoltage of 13.56 V and an on/off ratio of 5.73×106. As a result, We applied experimental for flexible PET substrate and showed that can be used to ZnO TFTs for flexible application.

본 논문은 메탈 이중층 전극을 이용한 유기 박막 트랜지스터를 제작하여 Au나 Ag 금속만으로 제작한 일반적인 유기 박막 트랜지스터와의 전기적 특성을 비교하였다. 전기적 특성에서 게이트 절연층은 높은 K 값을 갖는 Al2O3를 사용하였고, 유기 반도체층은 펜타센을 사용하였다. 본 실험에서 제작한 유기 박막 트랜지스터는 1.6 × 10-1 cm2의 포화영역 이동도를 얻을 수 있었으며, 또한 드레인 전압을 -5V로 하고, 게이트 전압을 3 V에서 -10 V 까지 인가하였을 때 3×105의 전멸 비를 얻을 수 있었다.

Silicon dioxide as gate dielectrics was grown at 400˚C on a polycrystalline Si substrate by inductively coupled plasma oxidation using a mixture of O2 and N2O to improve the performance of polycrystalline Si thin film transistors. In conventional high-temperature N2O annealing, nitrogen can be supplied to the Si/SiO2 interface because a NO molecule can diffuse through the oxide. However, it was found that nitrogen cannot be supplied to the Si/SiO2 interface by plasma oxidation as the N2O molecule is broken in the plasma and because a dense Si-N bond is formed at the SiO2 surface, preventing further diffusion of nitrogen into the oxide. Nitrogen was added to the Si/SiO2 interface by the plasma oxidation of mixtures of O2/N2O gas, leading to an enhancement of the field effect mobility of polycrystalline Si TFTs due to the reduction in the number of trap densities at the interface and at the Si grain boundaries due to nitrogen passivation.

Indium Gallium Zinc Oxide (IGZO) thin films were deposited onto 300 nm-thick oxidized Si substrates and glass substrates by direct current (DC) magnetron sputtering of IGZO targets at room temperature. FESEM and XRD analyses indicate that non-annealed and annealed IGZO thin films exhibit an amorphous structure. To investigate the effect of an annealing treatment, the films were thermally treated at 300˚C for 1hr in air. The IGZO TFTs structure was a bottom-gate type in which electrodes were deposited by the DC magnetron sputtering of Ti and Au targets at room temperature. The non-annealed and annealed IGZO TFTs exhibit an Ion/Ioff ratio of more than 105. The saturation mobility and threshold voltage of nonannealed IGZO TFTs was 4.92×10-1cm2/V·s and 1.46V, respectively, whereas these values for the annealed TFTs were 1.49×10-1cm2/V· and 15.43V, respectively. It is believed that an increase in the surface roughness after an annealing treatment degrades the quality of the device. The transmittances of the IGZO thin films were approximately 80%. These results demonstrate that IGZO thin films are suitable for use as transparent thin film transistors (TTFTs).

Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.

본 논문에서는 용액 공정을 이용한 고분자 절연층을 갖는 top-gate 구조의 펜타센 박막 트랜지스터(Thin Film Transistor, TFT)의 특성을 연구하였다. Top-gate 구조의 펜타센 TFT 제작에 앞서 유기 반도체인 펜타센의 결정성 성장을 돕기 위해서 가교된 PVP (cross-linked poly(4-vinylphenol))를 유리 기판 상에 스핀 코팅을 이용하여 형성한 후, 노광 공정을 통해 니켈/은 구조를 갖는 채널 길이 10μm의 소오스, 드레인 전극을 형성하였다. 그리고 열 증착을 이용하여 60 nm 두께의 펜타센 층을 성막하였고, 고분자 절연체로서 PVA(polyvinyl alchol) 또는 가교된 PVA를 용액공정인 스핀 코팅을 이용하여 형성한 후 열 증착으로 알루미늄 게이트 전극을 성막하였다. 이로써 제작된 소자들의 전기적 특성을 확인한 결과 가교된 PVA를 사용한 펜타센 TFT 보다 PVA를 게이트 절연체로 사용한 소자가 전기적 특성이 우수한 것으로 관찰되었다. 이는 PVA의 가교 공정에 의한 펜타센 박막의 성능 퇴화에 기인한 것으로 사료된다. 실험 결과 0.9μm 두께의 PVA 게이트 절연막을 사용한 top-gate 구조의 펜타센 TFT의 전계 효과 이동도와 문턱전압, 그리고 전류 점멸비는 각각, 약 3.9×10-3 cm2/Vs, -11.5 V, 3×105으로써 본 연구에서 제안된 소자가 용액 공정형 top-gate 유기 TFT 소자로서 우수한 성능을 나타냄을 알 수 있었다.