Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide whichcan enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was thenprepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a NiCl2 environment. Afterremoving surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemicalvapor deposition at 200oC. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing(RTA) process at 730oC for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as thecrystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer wasepitaxially crystallized with the help of NiSi2 precipitates that originated from the poly-Si seed layer. The crystallinity of theSERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process.The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to 1×1018cm−3. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by theSERTA process were 85cm2/V·s and 1.23V/decade at Vds=−3V, respectively. The off current was little increased underreverse bias from 1.0×10−11 A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakagecurrent can be fabricated with more precise experiments.

A high-quality CIGS film with a selenization process needs to be developed for low-cost and large-scale production. In this study, we used Cu2In3, CuGa and Cu2Se sputter targets for the deposition of a precursor. The precursor deposited by sputtering was selenized in Se vapor. The precursor layer deposited by the co-sputtering of Cu2In3, CuGa and Cu2Se showed a uniform distribution of Cu, In, Ga, and Se throughout the layer with Cu, In, CuIn, CuGa and Cu2Se phases. After selenization at 550˚C for 30 min, the CIGS film showed a double-layer microstructure with a large-grained top layer and a small-grained bottom layer. In the AES depth profile, In was found to have accumulated near the surface while Cu had accumulated in the middle of the CIGS film. By adding a Cu-In-Ga interlayer between the co-sputtered precursor layer and the Mo film and adding a thin Cu2Se layer onto the co-sputtered precursor layer, large CIGS grains throughout the film were produced. However, the Cu accumulated in the middle of CIGS film in this case as well. By supplying In, Ga and Se to the CIGS film, a uniform distribution of Cu, In, Ga and Se was achieved in the middle of the CIGS film.

In this study, chemical bath deposited (CBD) indium sulfide buffer layers were investigated as a possible substitution for the cadmium sulfide buffer layer in CIGS thin film solar cells. The performance of the In2S3/CIGS solar cell dramatically improved when the films were annealed at 300˚C in inert gas after the buffer layer was grown on the CIGS film. The thickness of the indium sulfide buffer layer was 80 nm, but decreased to 60 nm after annealing. From the X-ray photoelectron spectroscopy it was found that the chemical composition of the layer changed to indium oxide and indium sulfide from the as-deposited indium hydroxide and sulfate states. Furthermore, the overall atomic concentration of the oxygen in the buffer layer decreased because deoxidation occurred during annealing. In addition, an In-thin layer was inserted between the indium sulfide buffer and CIGS in order to modify the In2S3/CIGS interface. The In2S3/CIGS solar cell with the In interlayer showed improved photovoltaic properties in the Jsc and FF values. Furthermore, the In2S3/CIGS solar cells showed higher quantum efficiency in the short wavelength region. However, the quantum efficiency in the long wavelength region was still poor due to the thick buffer layer.

The selenization process has been a promising method for low-cost and large-scale production of high quality CIGS film. However, there is the problem that most Ga in the CIGS film segregates near the Mo back contact. So the solar cell behaves like a CuInSe2 and lacks the increased open-circuit voltage. In this study we investigated the Ga distribution in CIGS films by using the Ga2Se3 layer. The Ga2Se3 layer was applied on the Cu-In-Ga metal layer to increase Ga content at the surface of CIGS films and to restrict Ga diffusion to the CIGS/Mo interface with Ga and Se bonding. The layer made by thermal evaporation was showed to an amorphous Ga2Se3 layer in the result of AES depth profile, XPS and XRD measurement. As the thickness of Ga2Se3 layer increased, a small-grained CIGS film was developed and phase seperation was showed using SEM and XRD respectively. Ga distributions in CIGS films were investigated by means of AES depth profile. As a result, the [Ga]/[In+Ga] ratio was 0.2 at the surface and 0.5 near the CIGS/Mo interface when the Ga2Se3 thickness was 220 nm, suggesting that the Ga2Se3 layer on the top of metal layer is one of the possible methods for Ga redistribution and open circuit voltage increase.

In high-efficiency Cu(In,Ga)Se2 solar cells, Na is doped into a Cu(In,Ga)Se2 light-absorbing layer from sodalime-glass substrate through Mo back-contact layer, resulting in an increase of device performance. However, this supply of sodium is limited when the process temperature is too low or when a substrate does not supply Na. This limitation can be overcome by supplying Na through external doping. For Na doping, an NaF interlayer was deposited on Mo/glass substrate. A Cu(In,Ga)Se2 absorber layer was deposited on the NaF interlayer by a three-stage co-evaporation process As the thickness of NaF interlayer increased, smaller grain sizes were obtained. The resistivity of the NaF-doped CIGS film was of the order of 103Ω·cm indicating that doping was not very effective. However, highest conversion efficiency of 14.2% was obtained when the NaF thickness was 25 nm, suggesting that Na doping using an NaF interlayer is one of the possible methods for external doping.

Silicon dioxide as gate dielectrics was grown at 400˚C on a polycrystalline Si substrate by inductively coupled plasma oxidation using a mixture of O2 and N2O to improve the performance of polycrystalline Si thin film transistors. In conventional high-temperature N2O annealing, nitrogen can be supplied to the Si/SiO2 interface because a NO molecule can diffuse through the oxide. However, it was found that nitrogen cannot be supplied to the Si/SiO2 interface by plasma oxidation as the N2O molecule is broken in the plasma and because a dense Si-N bond is formed at the SiO2 surface, preventing further diffusion of nitrogen into the oxide. Nitrogen was added to the Si/SiO2 interface by the plasma oxidation of mixtures of O2/N2O gas, leading to an enhancement of the field effect mobility of polycrystalline Si TFTs due to the reduction in the number of trap densities at the interface and at the Si grain boundaries due to nitrogen passivation.

사이클로펜타디에닐 디카보닐 코발트 (Co(η(sup)5-C(sub)5H(sub)5) (CO2)의 반응성 화학 기상 증착법에 의해 600˚C 근처의기판온도에서 (100)Si 기판 위에 균일한 에피택셜 CoSi2 층이 후열처리를 거치지 않고 직접 성장되었다. (100) Si 기판 위에서 에피택셜 CoSi(sub)2 층의 성장 속도론을 575˚C에서 650˚C의 온도 구간에서 조사하였다. 증착 초기 단계에서 판(plate)모양의 CoSi(sub)2 스차이크가 쌍정의 구조를 가지고 (100) Si 기판에서<111> 방향을 따라서 불연속적으로 핵생성되었다. 111과 (100)면을 가진 불연속의 CoSi(sub)2 판은 (100) Si 위에서 평평한 계면으로 이루어진 에피택셜 층으로 성장했다. (100) Si 위에서 에피택셜 CoSi(sub)2 층을 통한 Co의 확산에 의해 제어되는 것으로 나타났다.

본 연구에서는 도핑하지 않은 다이아몬드 박막에서의 전류전도 경로를 체계적으로 규명하고 다이아몬드 박막의 전도기구에 대해 조사하였다. 도핑되지 않은 다결정 다이아몬드 박막에서 두께와 측정방향에 따른 교류 임피던스법에 의해 측정된 저향값이 기존의 표면전도 모델과는 일치하지 안니하였다. 다이아몬드 박막에 구리를 전기도금한 결과 구리는 결정립계에만 불연속적으로 도금되었고 다이아몬드 박막 위에 은을 증착한 후 전지에칭을 한 결과 결정립계가 우선 에칭이 되어 전류가 결정립계를 통하여 흐름을 확인하였다. 또, 리본형 다이아몬드 박막의 표면을 절연층으로 형성시킨 후 박막 내부의 결정립계를 통하여 전류가 흘러 전기도금이 되는 것으로부터 다결정 다이아몬드 박막의 주요 전기전도 경로는 결정립계임을 확인하였다. 높은 전기전도도를 보여주는 다이아몬드 박막은 전도 활성화 에너지가 45meV 정도이었고 dangling bond 밀도는 낮았다. 그러나 산소 열처리나 수소플라즈마처리가 Si passivation 이론과는 반대로 dangling bond 밀도를 증가시키면서 전기전도성을 떨어뜨렸다. 이 결과들과 표면의 탄소화학결합을 연결시켜 높은 전도성을 야기시키는 결합은 H-C-C-H 결합임을 추론하였다.