Waste SiC powders obtained from silicon wafer sludge have very low density and a narrow particle size distribution of 10-20 μm. A scarce yield of C and Si is expected when SiC powders are incorporated into the Fe melt without briquetting. Here, the briquetting variables of the SiC powders are studied as a function of the sintering temperature, pressure, and type and contents of the binders to improve the yield. It is experimentally confirmed that Si and C from the sintered briquette can be incorporated effectively into the Fe melt when the waste SiC powders milled for 30 min with 20 wt.% Fe binder are sintered at 1100oC upon compaction using a pressure of 250 MPa. XRF-WDS analysis shows that an yield of about 90% is obtained when the SiC briquette is kept in the Fe melt at 1650oC for more than 1 h.

The relationship the between electrical properties and surface roughness (Ra) of a wet-etched silicon wafer were studied. Ra was measured by an alpha-step process and atomic force microscopy (AFM) while varying the measuring range 10×10, 40×40, and 1000×1000μm. The resistivity was measured by assessing the surface resistance using a four-point probe method. The relationship between the resistivity and Ra was explained in terms of the surface roughness. The minimum error value between the experimental and theoretical resistivities was 4.23% when the Ra was in a range of 10×10μm according to AFM measurement. The maximum error value was 14.09% when the Ra was in a range of 40×40μm according to AFM measurement. Thus, the resistivity could be estimated when the Ra was in a narrow range.

The electrical properties and surface morphology changes of a silicon wafer as a function of the HF concentration as the wafer is etched were studied. The HF concentrations were 28, 30, 32, 34, and 36 wt%. The surface morphology changes of the silicon wafer were measured by an SEM (80˚ tilted at ×200) and the resistivity was measured by assessing the surface resistance using a four-point probe method. The etching rate increased as the HF concentration increased. The maximum etching rate 27.31 μm/min was achieved at an HF concentration of 36 wt%. A concave wave formed on the wafer after the wet etching process. The size of the wave was largest and the resistivity reached 7.54 ohm·cm at an 30 wt% of HF concentration. At an HF concentration of 30 wt%, therefore, a silicon wafer should have good joining strength with a metal backing as well as good electrical properties.

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafers. It is observed that the passivation quality of a-Si:H thin-films on c-Si wafers depends highly on the initial H-termination properties of the wafer surface. The effective minority carrier lifetime (MCLT) of highly H-terminated wafer is beneficial for obtaining high quality passivation of a-Si:H/c-Si. The wafers passivated by p(n)-doped a-Si:H layers have low MCLT regardless of the initial H-termination quality. On the other hand, the MCLT of wafers incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with initial cleaning and H-termination schemes. By applying the improved cleaning processes, we can obtain an MCLT of 100μsec after H-termination and above 600μsec after i a-Si:H thin film deposition. By adapting improved cleaning processes and by improving passivation and doped layers, we can fabricate a-Si:H/c-Si heterojunction solar cells with an active area conversion efficiency of 18.42%, which cells have an open circuit voltage of 0.670V, short circuit current of 37.31 mA/cm2 and fill factor of 0.7374. These cells show more than 20% pseudo efficiency measured by Suns-Voc with an elimination of series resistance.

실리콘 웨이퍼 직접 접합을 성공하기 위해서는 양호한 접합면을 구성하여야 하며, 이를 위해 접합면에서 발생하는 주요 결함 중 하나인 기포형 접합 결함을 억제하여야 한다. 본 연구에서는 접합면에서 발생하는 기포형 결함의 상온 접합 및 열처리 과정에서의 거동을 관찰하여 내부의 압력이 증가함을 직접 관찰할 수 있었다. 또한, 대기압 하의 열처리에서 결함이 발생하지 않는 SiO2-SiO2 접합 웨이퍼가 진공에서의 열처리에서 결함이 발생하는 현상을 통해 기포형 결함의 내부 압력과 성장과의 관계를 실험을 통하여 증명할 수 있었다.

고 에너지 (1.5 MeV) 이온 주입된 Boron의 농도와 silicon 기판의 초기 산소 농도의 변화에 따라 silicon기판에 형성된 결정 결함 및 금속 불순물의 Gettering 효율에 대하여 DLTS(Deep Level Transient Spectroscopy), SIMS(Secondary ion Mass Spectroscopy), BMD(Bulk Micro-Defect) analysis 및 TEM (Transmission Electron Microscopy)을 이용하여 연구하였다. 이온 주입 전후의 DLTS 결과를 확산로 및 RTA를 이용한 열처리 전후의 DLTS 결과와 비교할 때 이온 주입 전 시편에서 볼 수 있는 공공에 의한 깊은 준위는 열처리 온도의 증가에 따라 금속 불순물과 관련된 깊은 준위로 천이함을 알 수 있다. 또한 고온 열처리의 경우, 초기 산소 농도가 높을수록 깊은 준위의 농도가 감소함을 볼 때 초기 산소 농도가 높을 수록 gettering 효율 측면에서 유리한 것으로 사료된다

We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-H2O2 and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-H2O2 solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-H2O2 solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-H2O2 solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-H2O2 solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-H2O2 solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the NH4OH-H2O2-H2O and HCl-H2O2-H2O cleaning.

반도체 소자가 점점 고집적회되고 고성능화되면서 Si 기판 세정 방법은 그 중요성이 더욱 더 커지고 있다. 특히 ULSI급 소자에서는 세정 방법이 소자 생산수율 및 신뢰성에 큰 영향을 끼치고 있다. 본 연구에서는 HF-last 세정에 UV/O3과 SC-1 세정을 삽입하여 그 영향을 관찰하였다. 세정 방법은 HF-last 세정을 기본으로 split 1(piranha+HF), split 2(piranha+UV/O3+HF), split 3(piraha+SC-1+HF), split 4(piranha+(UV/O3+HF) x3회 반복)의 4가지 세정 방법으로 나누어 실험하였다. 세정을 마친 Si 기판은 Total X-Ray Fluorescence Spectroscopy(AFM)을 사용하여 표면거칠기를 측정하였다. 또한 세정류량을 측정하고, Atomic Force Microscopy(AFM)을 사용하여 표면거칠기를 측정하였다. 또한 세정후 250Å의 gate 산화막을 성장시켜 전기적 특성을 측정하였다. UV/O3을 삽입한 split 2와 split 4세정방법이 물리적, 전기적 특성에서 우수한 특성을 나타냈고, SC-1을 삽입한 split 3세정 방법이 표준세정인 split 1세정 방법보다 우수하지 못한 결과를 나타냈다.