To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

In this study, we intend to develop a control valve with oxidation resistance for hydrogen fluoride that can be applied to the semiconductor production process. Operated Valves currently in use is a form of assembling an air cylinder to the valve body. These valves generally have a cylinder body made of aluminum (Al), so they may corrode depending on the external environment, and the solution leaks along the rod inside the cylinder, causing damage to parts due to corrosion. To solve this problem, the valve plug shape was developed by devising and applying a plug using a valve different from the existing method, and it is possible to block the inflow of hydrogen fluoride into the valve control unit, thereby preventing damage to parts as well as maintaining stable valve operation.

The surface of silicon dummy wafers is contaminated with metallic impurities owing to the reaction with and adhesion of chemicals during the oxidation process. These metallic impurities negatively affect the device performance, reliability, and yield. To solve this problem, a wafer-cleaning process that removes metallic impurities is essential. RCA (Radio Corporation of America) cleaning is commonly used, but there are problems such as increased surface roughness and formation of metal hydroxides. Herein, we attempt to use a chelating agent (EDTA) to reduce the surface roughness, improve the stability of cleaning solutions, and prevent the re-adsorption of impurities. The bonding between the cleaning solution and metal powder is analyzed by referring to the Pourbaix diagram. The changes in the ionic conductivity, H2O2 decomposition behavior, and degree of dissolution are checked with a conductivity meter, and the changes in the absorbance and particle size before and after the reaction are confirmed by ultraviolet-visible spectroscopy (UV-vis) and dynamic light scattering (DLS) analyses. Thus, the addition of a chelating agent prevents the decomposition of H2O2 and improves the life of the silicon wafer cleaning solution, allowing it to react smoothly with metallic impurities.

Surface plasmon resonance is the resonant oscillation of conduction electrons at the interface between negative and positive permittivity material stimulated by incident light. In particular, when light transmits through the metallic microhole structures, it shows an increased intensity of light. Thus, it is used to increase the efficiency of devices such as LEDs, solar cells, and sensors. There are various methods to make micro-hole structures. In this experiment, micro holes are formed using a wet chemical etching method, which is inexpensive and can be mass processed. The shape of the holes depends on crystal facets, temperature, the concentration of the etchant solution, and etching time. We select a GaAs(100) single crystal wafer in this experiment and satisfactory results are obtained under the ratio of etchant solution with H2SO4:H2O2:H2O = 1:5:5. The morphology of micro holes according to the temperature and time is observed using field emission - scanning electron microscopy (FE-SEM). The etching mechanism at the corners and sidewalls is explained through the configuration of atoms.

To realize large-format compact array detectors covering a wide far-infrared wavelength range up to 200 μm, we have been developing Blocked-Impurity-Band (BIB) type Ge detectors with the room- temperature surface-activated wafer bonding technology provided by Mitsubishi Heavy Industries. We fabricated various types of p+-i junction devices which possessed a BIB-type structure, and evaluated their spectral response curves using a Fourier transform spectrometer. From the Hall effect measurement, we also obtained the physical characteristics of the p+ layers which constituted the p+-i junction devices. The overall result of our measurement shows that the p+-i junction devices have a promising applicability as a new far-infrared detector to cover a wavelength range of 100-200 μm.

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers’ orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

Waste SiC powders obtained from silicon wafer sludge have very low density and a narrow particle size distribution of 10-20 μm. A scarce yield of C and Si is expected when SiC powders are incorporated into the Fe melt without briquetting. Here, the briquetting variables of the SiC powders are studied as a function of the sintering temperature, pressure, and type and contents of the binders to improve the yield. It is experimentally confirmed that Si and C from the sintered briquette can be incorporated effectively into the Fe melt when the waste SiC powders milled for 30 min with 20 wt.% Fe binder are sintered at 1100oC upon compaction using a pressure of 250 MPa. XRF-WDS analysis shows that an yield of about 90% is obtained when the SiC briquette is kept in the Fe melt at 1650oC for more than 1 h.

This study is a development of a system for measuring the surface resistance of wafer and LCD by utilizing a three-axis positioner. Previous wafer measuring system is a developed product for measuring a wafer surface resistance. This is developed very long time. This is not a real action that it is needed a persistence development.. So, that is effected as weak point by simple mechanism and old software. This product is forecasted not being risen in world market. Therefore, this new product(surface measuring system by three axis positioner type) through this research is off the point a previous one axis revolute type, this new product is forecasted capable of a measurement not only wafer but also LCD.

In this study, in order to improve the efficiency of n-type monocrystalline solar cells with an Alu cell structure, we investigate the effect of the amount of Al paste in thin n-type monocrystalline wafers with thicknesses of 120 μm, 130 μm, 140 μm. Formation of the Al doped p+ layer and wafer bowing occurred from the formation process of the Al back electrode was analyzed. Changing the amount of Al paste increased the thickness of the Al doped p+ layer, and sheet resistivity decreased; however, wafer bowing increased due to the thermal expansion coefficient between the Al paste and the c-Si wafer. With the application of 5.34 mg/cm2 of Al paste, wafer bowing in a thickness of 140 μm reached a maximum of 2.9 mm and wafer bowing in a thickness of 120 μm reached a maximum of 4 mm. The study’s results suggest that when considering uniformity and thickness of an Al doped p+ layer, sheet resistivity, and wafer bowing, the appropriate amount of Al paste for formation of the Al back electrode is 4.72 mg/cm2 in a wafer with a thickness of 120 μm.

Physical and chemical changes in a polished wafer and in 2.5μm & 4μm epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for SiO2 removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished 2.5μm and 4μm Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, 2.5μm and 4μm, due to the meaningful differences in the initial surface chemical and physical properties.

The relationship the between electrical properties and surface roughness (Ra) of a wet-etched silicon wafer were studied. Ra was measured by an alpha-step process and atomic force microscopy (AFM) while varying the measuring range 10×10, 40×40, and 1000×1000μm. The resistivity was measured by assessing the surface resistance using a four-point probe method. The relationship between the resistivity and Ra was explained in terms of the surface roughness. The minimum error value between the experimental and theoretical resistivities was 4.23% when the Ra was in a range of 10×10μm according to AFM measurement. The maximum error value was 14.09% when the Ra was in a range of 40×40μm according to AFM measurement. Thus, the resistivity could be estimated when the Ra was in a narrow range.

The electrical properties and surface morphology changes of a silicon wafer as a function of the HF concentration as the wafer is etched were studied. The HF concentrations were 28, 30, 32, 34, and 36 wt%. The surface morphology changes of the silicon wafer were measured by an SEM (80˚ tilted at ×200) and the resistivity was measured by assessing the surface resistance using a four-point probe method. The etching rate increased as the HF concentration increased. The maximum etching rate 27.31 μm/min was achieved at an HF concentration of 36 wt%. A concave wave formed on the wafer after the wet etching process. The size of the wave was largest and the resistivity reached 7.54 ohm·cm at an 30 wt% of HF concentration. At an HF concentration of 30 wt%, therefore, a silicon wafer should have good joining strength with a metal backing as well as good electrical properties.

In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage (Voc) was observed when the wafer thickness was thinned from 170μm to 50μm. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied Voc of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for 50μm c-Si substrate, and 0.704 V for 170μm c-Si. The Voc in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of Voc in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.

웨이퍼를 위한 생산 라인이 중설되었을 경우 현재 가지고 있는 라인을 기반으로 하여 시간과 생산량을 조사한 수 5M라인과 50M 라인의 문제점을 파악하고 각 공정별 대기시간과 재고를 파악하여 최적의 생산라인을 만들 수 있게 한다. Simulation은 ARENA를 사용하였으며 시간과 생산 수량의 Data는 기존의 생산라인에서 조사하였다. 새로운 생산 라인을 증설할 때 가장 큰 문제점인 재고와 라인 평준화 부분에 대한 자료가 Simulation을 통하여 나타나져 문제 분석이 효율적으로 이루어 질수 있으나 통계적인 예측을 하기에는 시간이 너무 짧아 기계의 평균적인 작업 시간과 이동시간을 가지고 작품을 만들었으며, 사실과 근사한 값을 가지도록 노력을 하였다. 그 결과, 가동률연과 WIP부분에서 문제점이 발생을 하는 것을 찾을 수 있었으며 이결과를 바탕으로 실제 생산라인을 설계함에 있어 도움을 줄 수 있다. Solar Wafer 생산라인은 표준화가 이루어져 있지 않으며 자동화 또한 이루어져 있지 않아 많은 생산을 하는데 어려움이 있으며 공정의 최적화를 찾기 힘든 부분에 대한 생산라인의 문제점을 파악하여 라인의 평준화에 도움을 줄 수 있으며 생산되기 전 월별 주별 생산량을 미리 파악하여 생산관리에 도움을 줄 것이라 기대된다.

The structure and morphology of epitaxial layer defects in epitaxial Si wafers produced by the Czochralski methodwere studied using focused ion beam (FIB) milling, scanning electron microscopy (SEM), and transmission electron microscopy(TEM). Epitaxial growth was carried out in a horizontal reactor at atmospheric pressure. The p-type Si wafers were loaded intothe reactor at about 800oC and heated to about 1150oC in H2. An epitaxial layer with a thickness of 4µm was grown at atemperature of 1080-1100oC. Octahedral void defects, the inner walls of which were covered with a 2-4nm-thick oxide, weresurrounded mainly by 111 planes. The formation of octahedral void defects was closely related to the agglomeration ofvacancies during the growth process. Cross-sectional TEM observation suggests that the carbon impurities might possibly berelated to the formation of oxide defects, considering that some kinds of carbon impurities remain on the Si surface duringoxidation. In addition, carbon and oxygen impurities might play a crucial role in the formation of void defects during growthof the epitaxial layer.

In the environment of 450mm wafers production known as the next-generation semiconductor production process, one of the most significant features is the full automation over the whole manufacturing processes involved. The full automation system for 450mm